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Altera_Forum's avatar
Altera_Forum
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9 years ago

[HDL 9-806] Syntax error near "library IEEE".

I just started learning VHDL. The syntax I already have an my code is correct according to research I have done, but I keep getting this error that won't let me synthesis my code. I have pasted my code for you to look at. I am trying to turn on LED 15 of a NEXYS 4 when a person flips the switch. As a side note if anyone knows any resource to help learn VHDL that would be much appreciated.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company:

// Engineer:

//

// Create Date: 09/09/2016 01:21:54 PM

// Design Name:

// Module Name: LED15

// Project Name:

// Target Devices:

// Tool Versions:

// Description:

//

// Dependencies:

//

// Revision:

// Revision 0.01 - File Created

// Additional Comments:

//

//////////////////////////////////////////////////////////////////////////////////

module LED15(

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity my_entity is

port(

switch : in STD_LOGIC;

light_LED : out STD_LOGIC

);

end my_entity;

architecture Behavioral of my_arch of my_entity is

begin

if (switch = 1) then

port_light_LED <= '1';

end if;

end Behavioral;

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    The library declaration needs to be outside the module. Also, the 'timescale statement might not be legal. I'm not sure, but I never use them in files fed to Quartus. It should go in the test bench, not in synthesized code.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    `timescale and module are Verilog keywords, but your code is VHDL. Also in VHDL (pre 2008) comments are marked with --, not //

    Remove the `timescale, module lines and // comments
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    It looks like he might have done new->verilog file and filled it with VHDL.