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Honored Contributor[HDL 9-806] Syntax error near "library IEEE".
I just started learning VHDL. The syntax I already have an my code is correct according to research I have done, but I keep getting this error that won't let me synthesis my code. I have pasted my co...
Altera_ForumHonored Contributor
Honored Contributor`timescale and module are Verilog keywords, but your code is VHDL. Also in VHDL (pre 2008) comments are marked with --, not //
Remove the `timescale, module lines and // comments
