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Altera_Forum
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9 years ago

[HDL 9-806] Syntax error near "library IEEE".

I just started learning VHDL. The syntax I already have an my code is correct according to research I have done, but I keep getting this error that won't let me synthesis my code. I have pasted my co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

`timescale and module are Verilog keywords, but your code is VHDL. Also in VHDL (pre 2008) comments are marked with --, not //

Remove the `timescale, module lines and // comments