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sumanth1's avatar
sumanth1
Icon for New Contributor rankNew Contributor
2 years ago

GPIO INTEL IP IN DDR MODE NOT ABLE TO FIT IN IO BANK OF AGILEX FPGA (AGFB012R24B2I3E)

I have used gpio intel ip in DDR mode for agilex ( AGFB012R24B2I3E) fpga in 2D bank. it is showing "Error(175005): Could not find a location with: GPIO_SHARED_SRESET of 6950 (1 location affected)" for 9 locations. when i am using signal tap only this fitter error is showing .

can please explain what could be the reason for it ?

Compilation
Hdl
Platform

2 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hello


    Thank you for submitting your question in Intel Community.

    I'm Adzim will assist you in this forum.


    The error message shown that there are no possible location for that signal to fit into particular IO Bank.

    It's may be due to the pin location already being occupied by other signals.

    It's also may related to other IP cannot share the IO Bank with other IP as well.


    BTW, I found a KDB that might be related to your issue.

    Please check the KDB and let me know if it's help to resolve your issue.

    Link: https://www.intel.com/content/www/us/en/support/programmable/articles/000086663.html


    Regards,

    Adzim



  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.