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Altera_Forum's avatar
Altera_Forum
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17 years ago

Global clock networks in Cyclone II

Hi this are fairly simple questions I believe but I'm a bit new with Quartus II.

I have a design where I'm producing a 100MHz clock signal using output c0 of a PLL. That is my system_clk signal which is the clock for many components in my design.

How can I tell Quartus to route that signal through an internal global clock network (or is it automatically done)? Do I need to instantiate a clock control block?

I also have an asynchronous reset that comes into an input pin in the FPGA and again is connected to several of my components (plus is my nios reset). Should I also use a global clock network for it? If so, how do I specify that to Quartus?

Cheers

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    All these actions are performed by Quartus automaticly (in a usual design).

    Depending on your design, it may be useful to synchronize the asynchronous reset, to get an internal reset that is asserted asynchronously but released clock synchronous. The Quartus Handbook and other documents are discussing the topic in detail. Otherwise, you get a finite prohability that counter or state machines are reset to an unwanted or even illegal state.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    The altclkctrl block can be instantiiated IF you want to use some of it's special features(like muxing or enable). But a global output always goes through the ctrlblock and onto a global(unless it's a dedicated output). You won't see GLOBAL or anything in the TimeQuest report, but you should see the CLKCTRL block if you do a report_timing -detail full_path.

    In the Fitter Report, there is also a section called Global Signals, which should have it listed there. As for forcing onto/off of global, I tend to let Quartus make it's decisions, and only if I think it did something wrong will I modify it. With your system having one clock and one reset, they'll probably both go on globals and that's what you want.

    Here's a doc about Recovery/Removal timing, which is basically understanding reset and recovery. Probably more than you asked, but thought I'd link it:

    http://www.alteraforum.com/forum/showthread.php?t=2158&highlight=recovery
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    As for forcing onto/off of global, I tend to let Quartus make it's decisions, and only if I think it did something wrong will I modify it. With your system having one clock and one reset, they'll probably both go on globals and that's what you want.

    --- Quote End ---

    There's an exception where you don't want a reset using global routing. Even for a reset with high fan-out, nonglobal routing can be better than the big global buffer insertion delay for recovery and removal timing. If you get recovery or removal violations for paths that don't need to be cut, try setting "Global Signal" to "Off" in the Assignment Editor for that reset.