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Altera_Forum
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17 years ago

Global clock networks in Cyclone II

Hi this are fairly simple questions I believe but I'm a bit new with Quartus II. I have a design where I'm producing a 100MHz clock signal using output c0 of a PLL. That is my system_clk signal...
Altera_Forum's avatar
Altera_Forum
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17 years ago

All these actions are performed by Quartus automaticly (in a usual design).

Depending on your design, it may be useful to synchronize the asynchronous reset, to get an internal reset that is asserted asynchronously but released clock synchronous. The Quartus Handbook and other documents are discussing the topic in detail. Otherwise, you get a finite prohability that counter or state machines are reset to an unwanted or even illegal state.