Glitchs on a counter

Hi everybody

I m facing a problem with quartus II and modelsim-altera.

Here is my VHDL code :

library ieee ;use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
--use ieee.std_logic_unsigned.all;
use work.all;
---------------------------------------------
entity AD7960_Ctrl is
port(    
    m_clk_i:    in std_logic;                         --100MHz clock for timing    
    reset_n_i:    in std_logic;                        --reset signal active low    
    clk_o:        out std_logic                    --clock out    
);
end AD7960_Ctrl;
----------------------------------------------
architecture behavioral of AD7960_Ctrl is
constant    ADC_CYC_CNT            :    std_logic_vector(4 downto 0)     := "10011"  ;
signal    adc_tcyc_cnt:        std_logic_vector(4 downto 0);
begin
clk_o<= '1' when adc_tcyc_cnt = "00010" else '0' ;
process (m_clk_i,reset_n_i,adc_tcyc_cnt)
begin
    if (reset_n_i = '0') then
        adc_tcyc_cnt <= ADC_CYC_CNT;
    elsif (m_clk_i='1' and m_clk_i'Event)then
        if adc_tcyc_cnt /= "00000" then
        adc_tcyc_cnt <= std_logic_vector(unsigned(adc_tcyc_cnt) - 1) ;     
        else
        adc_tcyc_cnt <= ADC_CYC_CNT;
        end if ; 
    end if ;
end process;
end behavioral;

And here my test bench:

-- testbench for counter_3bit
-- Load Altera libraries for this chip
LIBRARY IEEE;
LIBRARY MAXII;
USE IEEE.STD_LOGIC_1164.ALL;
USE MAXII.MAXII_COMPONENTS.ALL;
entity ad7960_ctrl_tb is
end ad7960_ctrl_tb;
architecture testbench1 of ad7960_ctrl_tb is
signal  m_clk_i:         std_logic := '0';                         --100MHz clock for timing
signal     reset_n_i:       std_logic:= '0';                        --reset signal active low
signal     clk_o:             std_logic:= '0';                        --clock out
  constant clk_period_100 : time := 10ns;
  begin
    -- dut = device under test (same name as top project from Quartus)
    dut : entity work.ad7960_ctrl
      -- Map the ports from the dut to this testbench
      port map (
        m_clk_i=> m_clk_i , 
        
        reset_n_i=>    reset_n_i ,
                
        clk_o=>    clk_o        
           );
    
   -- Clock process definitions( clock with 50% duty cycle is generated here.
MAIN_CLK_process :process
begin
    m_clk_i<= not m_clk_i; wait for clk_period_100/2;
    
end process;
  stim_proc: process
   begin         
        
        wait for 13ns;
        reset_n_i <='1';
       
        wait;
  end process;
end ;

Here is the output waveforms:

http://www.alteraforum.com/forum/attachment.php?attachmentid=13105&stc=1

As you can see a have kind of glitchs on the output signal when my counter adc_tcyc_cnt goes from 0 to 19.

Critical warning in quartus are just :

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From m_clk_i (Rise) to m_clk_i (Rise) (setup and hold)

and warning are just :

Warning: Feature LogicLock is not available with your current license

Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

I if a change :

constant    ADC_CYC_CNT            :    std_logic_vector(4 downto 0)     := "10011"  ;

by (for exemple)

constant    ADC_CYC_CNT            :    std_logic_vector(4 downto 0)     := "10100"  ;

there is no problem.

I would apreciate any help

thanks.