Glitchs on a counter

I assume this is a post place and route simulation? These glitches occur because the clk_o signal is combinatorial.

Not all bits of the counter change at exactly the same time. So on the clock cycle with the glitch you momentarily get the value to match to output a 1 as the counter transitions back to 0.

To prevent these glitches you should register the clk_o output.

On a side note, why do you have an output called clk? Generating clicks on logic is not good practice and actually this doesn't look like a clock at all, more like a clock enable ( which is what you should generate).