Generic logic cells placement

Hi,

Thanks for your reply, but as you answer :

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I'd like the QII place the logic automatically.

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I can only say "I don't want the QII place the logic automatically".

I just want to know if there is a way to get the LAB Number, Name and Position.

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Hi,

Thanks for your reply, but as you answer :

I can only say "I don't want the QII place the logic automatically".

I just want to know if there is a way to get the LAB Number, Name and Position.

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I really don't know why you stuck to want place logic manually. However, you can find the logic resource coordinate system from QII easily, as attached image shows. Actually, you'll find it's very difficult to mach between your high level description language (such as VHDL) and the low level logic unit (such as LE. You need deeply into the netlist to do the position lock. It's a very large work.

Manual placement is not really recommended. What is the reason you want to use it? it is usually only used to help timing with key registers.

afaik, there is no command to get the setup of the device - you will have to create your own stats for this from the data-sheets.

Hi,

I understand that's a hard work to do. I already did it by hand, and I can't handle it anymore.

Anyway, i can only do the placement for one device into my tcl script if i can't get the LAB/LE/FF name/position/numbers.

The generic way could help me to compile (using my tcl script) the design for a family and device specified by a user,

and place "automatically" the design where he want to (restricted to bottom_left, bottom_right, top_left, top_right, middle or four_corners).

Edit :

I want to use manual placement to do testbenchs on various PUF architecture, and check which one is the best.

It's sad that I can't get the device's setup ...

Thanks for your help guys.

have you looked into logic lock regions? you can assign specific items (registers, whole entities etc) to specified regions within the device.

I still dont understand the reason for manual placement.

Hi,

I've been using Quartus backannotation to figure out how the logic in my designs is placed, and apply low-level constraints to timing-sensitive circuits.

You can run this command:

quartus_cdb --64bit <qpf_name> -c <qsf_name> --back_annotate=routing

It will generate a QSF file with the list of locations of FFs, RAMs, DSPs, IOs and all other primitives your design is using.

You can read more about quartus_cdb and backannotation options in Quartus documentations, or just google.

Thanks,

Evgeni