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Altera_Forum's avatar
Altera_Forum
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11 years ago

Generic logic cells placement

Hi all, I'm working on a tcl script to compile a small design where i can choose the position of different logic elements (such as bottom-left, top right, four corners, ...). I would l...
Altera_Forum's avatar
Altera_Forum
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11 years ago

Hi,

I've been using Quartus backannotation to figure out how the logic in my designs is placed, and apply low-level constraints to timing-sensitive circuits.

You can run this command:

quartus_cdb --64bit <qpf_name> -c <qsf_name> --back_annotate=routing

It will generate a QSF file with the list of locations of FFs, RAMs, DSPs, IOs and all other primitives your design is using.

You can read more about quartus_cdb and backannotation options in Quartus documentations, or just google.

Thanks,

Evgeni