Hello, I have been wondering for a while if it is possible to let some standard tool (like quartus, or ISE or maybe even a windows tool) generate a VHDL file from previous written VHDL code. For example when you have some different VHDL files you have written before, and theyre all reusable. Is it possible to say; I want these 3 files working together and now try and make a toplevel for me? Or do you have to write your own file in a different language that links them all together? I hope it is somewhat clear, but I can understand that it might be too vague, so please ask questions that might help making my question clear. Thanks in advance

You can write a top level in VHDL if you want. And SOPC Builder/QSys might be the closest thing to "auto generation" of a top level. But it still needs to know how you want things connected. But your question is not very clear. Yes you can write a top level in VHDL to instantiate and connect any number of other VHDL modules.

I see I wasn't very clear. The problem is that one way or another, this toplevel is going to be generated automatically. If there is no tool to do such a thing, it would become a self written program that would read all the inputs and outputs from the components and than decide how these things are going to be connected. In some way it seems like an impossible thing to do, since it needs to be really general. Thats why I hoped there would be some kind of tool to do such a thing. So that I dont have to write 20 different toplevels, for all the different designs I want to make(designs that might only differ one component for example). I'm not sure if you could ''speak'' to qsys via TCL? I try my best to make it less general, but it isn't as easy as i thought.

--- Quote Start --- The problem is that one way or another, this toplevel is going to be generated automatically. --- Quote End --- Think of it slightly differently. When you design a PCB and layout an FPGA, the pin functions of the FPGA are then fixed. You can create a single top-level design that represents all designs that will ever be used on the board. The pin names in this top-level design are then fixed and never change, so it makes creating .SDC constraints files a lot easier, since you only need to create them once and the pin names remain the same. Your "designs" are then one layer below this top-level, and yes, you have to manually connect them to the top-level pins on the FPGA. There really is no automated way to do this, since a tool cannot guess how you want the signals connected. --- Quote Start --- it would become a self written program that would read all the inputs and outputs from the components and than decide how these things are going to be connected. --- Quote End --- There's really no way that this can work the way you think. Lets say I have some I/O blocks, some memory, an SPI controller, and an I2C controller IP blocks. How can a program decide how these should be connected? You have to tell it, right? That is the purpose of SOPC Builder and Qsys. That tool produces a top-level component that describes the I/O of that one component. That component might be the top-level, or it might be one of many components in a design. Bottom line, you'll have to manually connect wires from your components to the top-level design that represents your FPGA pins. --- Quote Start --- In some way it seems like an impossible thing to do, since it needs to be really general. Thats why I hoped there would be some kind of tool to do such a thing. So that I dont have to write 20 different toplevels, for all the different designs I want to make(designs that might only differ one component for example). I'm not sure if you could ''speak'' to qsys via TCL? I try my best to make it less general, but it isn't as easy as i thought. --- Quote End --- If the top-level design that represents the FPGA is the same, and the pins on the Qsys component remain the same, then you can simply regenerate the Qsys instance. However, if your Qsys system has different pins, then those pins need to go somewhere, and you need to route them. If it was easier to control the pin names on the Qsys system, then you could map the top-level Qsys pins to the FPGA pins, however, your constraints file would have the top-level pin names change ... Take a look at the design files in this tutorial; http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial In this design, one Qsys file is used for multiple boards. I know, you probably want something slightly different, but take a look and get ideas. If you get stuck, ask questions, or describe your design(s) in more detail. Perhaps all you really need is some generate statements. Cheers, Dave

Thanks for the extensive explanation Dave. It is possible to import a pinmapping right? Than I would think the problem with not knowing how to put the signals together would be over, or am I thinkiing about this a little too easy? Let's say at least the inputs and outputs from the toplevel are always the same, but only the signalls vary with different components. I always have a component of type A, this component also always has the same in and outputs for every different component(so it only differs in architecture). And I also always have a component of type B, same inputs and outputs for every different component again. Now I always want to connect a (yet undifined)component of type C, to a component of type A. And a (yet undifined)component of type D also connects to type A and B. So we've got: C<>A<>D<>B Always Is it than still not possible to say: ok since we have type A we need to connect it with type C and we need to do it this way: input Ax <= output Cx, input Ay <= output Cy I am also reading the tutorial, so maybe I will get those answers there too

--- Quote Start --- It is possible to import a pinmapping right? --- Quote End --- Sure, but there still has to be a one-to-one mapping between the pin names in your top-level HDL entity and your pin mapping script or spreadsheet. If you look at the tutorial source, you will see that correspondence, i.e., a top-level HDL file and a Tcl script with pin constraints, where those constraints use the same name as the top-level HDL. If your top-level HDL is generated by Qsys, then the top-level pin names change depending on how you name the components in the system. --- Quote Start --- Than I would think the problem with not knowing how to put the signals together would be over, or am I thinking about this a little too easy? Let's say at least the inputs and outputs from the top-level are always the same, but only the signals vary with different components. I always have a component of type A, this component also always has the same in and outputs for every different component (so it only differs in architecture). And I also always have a component of type B, same inputs and outputs for every different component again. Now I always want to connect a (yet undefined) component of type C, to a component of type A. And a (yet undefined) component of type D also connects to type A and B. So we've got: C<>A<>D<>B Always Is it than still not possible to say: ok since we have type A we need to connect it with type C and we need to do it this way: input Ax <= output Cx, input Ay <= output Cy --- Quote End --- This problem can be solved using VHDL configurations. In VHDL a 'component' definition tells the compiler what pins a component has. Using a configuration you can map an entity to a component. In your code, you can write the code to include known components A and B, and connect them to 'component' definitions for C and D. Then you use a configuration to map C and D to their implementations. I posted a VHDL configurations example in this thread: http://www.alteraforum.com/forum/showthread.php?t=30414&page=2 Take a look at VHDL configurations and let me know if they meet your requirements. If they don't, we can discuss using generate statements, generics, and Tcl. Cheers, Dave

Generate VHDL code from VHDL code | Altera Community

34 Replies

Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I just meant to say, that I don't have the information about what this exact component should do.

--- Quote End ---

Why not? Even if a component is a black-box component provided by someone else, you can still write a testbench to ensure that it adheres to its interface standard, eg., if I wanted to check that an Altera Avalon-MM slave component worked correctly, I would use the Avalon-MM verification IP suite to test it.

--- Quote Start ---

but wait, what if this component isn't doing the right thing, I must at least tell the user it will not work.

--- Quote End ---

Any how do you tell if the component isn't doing the right thing if you do not test it?

Cheers,
Dave
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
if I wanted to check that an Altera Avalon-MM slave component worked correctly, I would use the Avalon-MM verification IP suite to test it
--- Quote End ---

That sounds not so weird indeed. The interface should be able to be tested without knowing what the exact component does. But I would never know if the answer the component supplies is of any logical value, unless I have written the design myself and know when it should give output y with input x. Thats where I was thinking.

--- Quote Start ---
Any how do you tell if the component isn't doing the right thing if you do not test it?
--- Quote End ---

That was the line where I was thinking about when I can start thinking about that testbench. Since I am still a bit stuck to design the thing itself, I cannot write a testbench yet. Because than I would have to know the exact design and think about how to define my generated design works.

How weird is it that I am thinking about using another language to read the entity inputs and outputs to know which ones I need to put in my toplevel?
So at that point I know which files i need to include, so I also know which entities. But I don't know which inputs and outputs the entity has and how can I connect this component if I don't know the in or outputs?
Or am I overseeing some features of VHDL? In my understandings I can use the generates when I already have instantiated the components and the same with configurations.
Altera_Forum
Honored Contributor
12 years ago
I thought I should say I have made my program very different than what I thought was possible.
I think indeed it is not possible, or very hard, to generate such a project all with just VHDL.
So I had made a program which could make such a design, I think that is possible in any software language.
I am not quite sure if it would be possible if the designs dont have any relations with each other.
Main point is indeed that you really need to know exactly what kind of designs need to be generated, otherwise you keep writing the wrong things and can't figure out whats the way to deal with it.

I didn't have time to write a testbench, so it is only 'tested' via the RTL design.

Thanks again Dave for the input you have given, maybe I haven't used the things you mentioned, but I sure learned a lot:)
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I thought I should say I have made my program very different than what I thought was possible.
--- Quote End ---

To some degree this is why writing an example, or prototype, is a good idea ... your ideas evolve as you write code.

--- Quote Start ---

I didn't have time to write a testbench, so it is only 'tested' via the RTL design.

--- Quote End ---

Take the time to write a testbench for each module. If each module has a standardized interface, eg., Avalon-MM or AXI, then once you have written the first testbench, the others are very simple.

--- Quote Start ---

Thanks again Dave for the input you have given, maybe I haven't used the things you mentioned, but I sure learned a lot:)
--- Quote End ---

You're welcome. I'm not bothered if you do not follow my advice, but eventually you'll figure out that some of it is good :)

Cheers,
Dave

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Generate VHDL code from VHDL code

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