Generate VHDL code from VHDL code

I thought I should say I have made my program very different than what I thought was possible.

I think indeed it is not possible, or very hard, to generate such a project all with just VHDL.

So I had made a program which could make such a design, I think that is possible in any software language.

I am not quite sure if it would be possible if the designs dont have any relations with each other.

Main point is indeed that you really need to know exactly what kind of designs need to be generated, otherwise you keep writing the wrong things and can't figure out whats the way to deal with it.

I didn't have time to write a testbench, so it is only 'tested' via the RTL design.

Thanks again Dave for the input you have given, maybe I haven't used the things you mentioned, but I sure learned a lot:)