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if I wanted to check that an Altera Avalon-MM slave component worked correctly, I would use the Avalon-MM verification IP suite to test it
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That sounds not so weird indeed. The interface should be able to be tested without knowing what the exact component does. But I would never know if the answer the component supplies is of any logical value, unless I have written the design myself and know when it should give output y with input x. Thats where I was thinking.
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Any how do you tell if the component isn't doing the right thing if you do not test it?
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That was the line where I was thinking about when I can start thinking about that testbench. Since I am still a bit stuck to design the thing itself, I cannot write a testbench yet. Because than I would have to know the exact design and think about how to define my generated design works.
How weird is it that I am thinking about using another language to read the entity inputs and outputs to know which ones I need to put in my toplevel?
So at that point I know which files i need to include, so I also know which entities. But I don't know which inputs and outputs the entity has and how can I connect this component if I don't know the in or outputs?
Or am I overseeing some features of VHDL? In my understandings I can use the generates when I already have instantiated the components and the same with configurations.
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