Generate VHDL code from VHDL code

--- Quote Start ---

I thought I should say I have made my program very different than what I thought was possible.

--- Quote End ---

To some degree this is why writing an example, or prototype, is a good idea ... your ideas evolve as you write code.

--- Quote Start ---

I didn't have time to write a testbench, so it is only 'tested' via the RTL design.

--- Quote End ---

Take the time to write a testbench for each module. If each module has a standardized interface, eg., Avalon-MM or AXI, then once you have written the first testbench, the others are very simple.

--- Quote Start ---

Thanks again Dave for the input you have given, maybe I haven't used the things you mentioned, but I sure learned a lot:)

--- Quote End ---

You're welcome. I'm not bothered if you do not follow my advice, but eventually you'll figure out that some of it is good :)

Cheers,

Dave