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Altera_Forum
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11 years ago

Generate a Test bench Output files .Vht

Hello

I use recently Quartus II 13.1

I would like generate a Test bench Output files .Vht from Waveform/vector File .VWf but I was unsuccessful .The file .vwf is a separate window from Quartus .

Before, I use Quartus II 7.2 and for to do that I generate a Waveform/vector File .VWf and from menu I click on the File => Export ,then it’s generate and open a Test bench Output files .Vht .

Could you tell me how I can generate a vht from vwf file fom quartus II 13.1? Thant you .

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Under Simulation menu, select "Generate ModelSim Testbench and script".

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Thank a lot Siraj Muhammad

    I have now another problem!

    When I do Generate modelsim Testbennh and script from Quartus 13.1, It generate verilog HDL file .

    Here’s how I do.

    I set the format output VHD from : settings=>EDA Tool Settings=>simulations=>EDA Netlist Writer Settings and after Apply.

    After I generate the waveform/vector File and as you told me, Under Simulation menu, select "Generate ModelSim Testbench and script". But, It generate verilog HDL file. When I return at the settings page I surprise to see that quartus change the format, it put Verilog HDL!

    Could you describe the different Steps for get the Format output Vht and not Vt. Thank you again
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Thank a lot Siraj Muhammad

    I have now another problem!

    When I do Generate modelsim Testbennh and script from Quartus 13.1, It generate verilog HDL file .

    Here’s how I do.

    I set the format output VHD from : settings=>EDA Tool Settings=>simulations=>EDA Netlist Writer Settings and after Apply.

    After I generate the waveform/vector File and as you told me, Under Simulation menu, select "Generate ModelSim Testbench and script". But, It generate verilog HDL file. When I return at the settings page I surprise to see that quartus change the format, it put Verilog HDL!

    Could you describe the different Steps for get the Format output Vht and not Vt. Thank you again

    --- Quote End ---

    Actually I don't have any idea about that, I have just moved to ModelSim because I found so many problems with the Waveform Simulator. Plus, there are many features that will benefit you. I recommend using ModelSim and learning how to write testbench.