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Thank a lot Siraj Muhammad
I have now another problem!
When I do Generate modelsim Testbennh and script from Quartus 13.1, It generate verilog HDL file .
Here’s how I do.
I set the format output VHD from : settings=>EDA Tool Settings=>simulations=>EDA Netlist Writer Settings and after Apply.
After I generate the waveform/vector File and as you told me, Under Simulation menu, select "Generate ModelSim Testbench and script". But, It generate verilog HDL file. When I return at the settings page I surprise to see that quartus change the format, it put Verilog HDL!
Could you describe the different Steps for get the Format output Vht and not Vt. Thank you again
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Actually I don't have any idea about that, I have just moved to ModelSim because I found so many problems with the Waveform Simulator. Plus, there are many features that will benefit you. I recommend using ModelSim and learning how to write testbench.
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