Generate a Test bench Output files .Vht

Thank a lot Siraj Muhammad

I have now another problem!

When I do Generate modelsim Testbennh and script from Quartus 13.1, It generate verilog HDL file .

Here’s how I do.

I set the format output VHD from : settings=>EDA Tool Settings=>simulations=>EDA Netlist Writer Settings and after Apply.

After I generate the waveform/vector File and as you told me, Under Simulation menu, select "Generate ModelSim Testbench and script". But, It generate verilog HDL file. When I return at the settings page I surprise to see that quartus change the format, it put Verilog HDL!

Could you describe the different Steps for get the Format output Vht and not Vt. Thank you again