Generate a pulse by using a counter/timer

Hello,

I just started with FPGAs and thus I am trying to improve my VHDL skills. Recently I am building a design that generates a pulse which is meant to start a ADC conversion. My idea is to use a counter which controls the pulse length. Unfortunately, the counter seems to start but never reaches the value at which the pulse should end. After several hours of trying I have no clue what is going wrong. May you could have a look at my code.

So this is my counter:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
    generic
    (
        n : natural := 1
    );
    
    port
    (
        clock : in std_logic;
        clock_enable : in std_logic;
        reset : in std_logic;
        output : out std_logic_vector((n-1) downto 0)
    );
end;
architecture behaviour of counter is
    signal counter_value : std_logic_vector((n-1) downto 0) := (others => '0');
    
begin
    
    process(clock, reset)
    begin
        if (reset = '1') then
            counter_value <= (others => '0');
        elsif (rising_edge(clock)) then
            if (clock_enable = '1') then
                counter_value <= counter_value + 1;
            end if;
        end if;
    end process;
    output <= counter_value;
end behaviour;

And here is my ADC design file, which uses the counter:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;
    
entity ti_ads1675 is
    port
    (
        -- ports required by the TI ADS1675
        start : out std_logic;
        
    
        -- ports required by the avalon-mm interface
        clock : in std_logic;
        reset_n : in std_logic;
        
        read : in std_logic;
        write: in std_logic;
        
        address: in std_logic;
        
        writedata : in std_logic_vector(31 downto 0);
        readdata : out std_logic_vector(31 downto 0)
    );
end ti_ads1675;
architecture rtl of ti_ads1675 is
    
    component counter is
        generic
        (
            n : natural := 1
        );
        port
        (
            clock                : in            std_logic;
            clock_enable    : in            std_logic;
            reset                : in            std_logic;
            output            :         out    std_logic_vector(n downto 0)
        );
    end component;
    
    -- counter related signals
    signal counter_clock_enable : std_logic := '0';
    signal counter_reset : std_logic := '1';
    signal counter_value : std_logic_vector(31 downto 0);
    
    -- general signals
    signal control_register : std_logic_vector(31 downto 0) := x"00000000";
    signal data_register : std_logic_vector(31 downto 0);
begin
    counter_inst : component counter
        generic map
        (
            n => 32
        )
        port map
        (
            clock    => clock,
            clock_enable => counter_clock_enable,
            reset => counter_reset,
            output => counter_value        
        );
    registers : process (clock)
    begin
        if (rising_edge(clock)) then
            -- reset registers
            if (reset_n = '0') then
                data_register <= x"00000000";
                control_register <= x"00000000";
                readdata <= x"00000000";
            -- read register contents
            elsif (read = '1') then
                if (address = '0') then
                    readdata <= data_register;
                elsif (address = '1') then
                    readdata <= control_register;
                end if;
            -- write register contents
            elsif (write = '1') then
                if (address = '0') then
                    data_register <= writedata;
                elsif (address = '1') then
                    control_register <= writedata;
                end if;
            end if;
        end if;
    end process registers;
    
    
    --------------------------
    -- gererate start pulse --
    --------------------------
    process (control_register(2), counter_value)
    begin
        if (rising_edge(control_register(2))) then
            counter_reset <= '0';
            counter_clock_enable <= '1';
            start <= '1';
        elsif (counter_value = x"0000ffff") then
            start <= '0';
            counter_clock_enable <= '0';
            counter_reset <= '1';
            control_register(2) <= '0';
        end if;
    end process;
end rtl;

I have absolutely no clue what is wrong here. The counter itself works, so I think I made a (logic?) fault in my ADC design file. I am thankful for any tips or hints.

Regards Michael