Forum Discussion
Altera_Forum
Honored Contributor
9 years agoHi, thank you for your fast replies. I'll have a closer look at your suggestions and try to change my code accordingly. I'll report the outcome...
... with your help I just go the design running. I build an edge detector an used it to start my counter. Here is the code:library ieee;
use ieee.std_logic_1164.all;
entity edge_detector is
port
(
clock : in std_logic;
signal_in : in std_logic;
output : out std_logic
);
end edge_detector;
architecture behavioral of edge_detector is
signal signal_delayed : std_logic;
begin
process (clock)
begin
if (rising_edge(clock)) then
signal_delayed <= signal_in;
end if;
end process;
output <= signal_in and (not signal_delayed);
end behavioral; And following the updated code snippet of the ADC-Design: process(control_register_start_edge, counter_value)
begin
if (control_register_start_edge = '1') then
counter_reset <= '0';
counter_clock_enable <= '1';
start <= '1';
elsif (counter_value = x"00000004") then
start <= '0';
counter_clock_enable <= '0';
counter_reset <= '1';
end if;
end process; I was able to verify the design with ModelSim and even used the 'start' signal to blink an LED on my BeMicro CV ;) No I am looking for a intelligent way to reset my register bit to '0' again. My first idea was to use a reset signal which would be detected in my r/w register process... So after all, thank you for your help!