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Altera_Forum's avatar
Altera_Forum
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9 years ago

Generate a pulse by using a counter/timer

Hello, I just started with FPGAs and thus I am trying to improve my VHDL skills. Recently I am building a design that generates a pulse which is meant to start a ADC conversion. My idea is to use ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi,

At least one problem is in line: 

if (rising_edge(control_register(2))) then

do not use rising_edge function to detect rising edge of general signal of your design. rising_edge function ment to be used for CLOCK edge detection.

Regards,