Generate a pulse by using a counter/timer

This is the culprit code:

--------------------------
    -- gererate start pulse --
    --------------------------
    process (control_register(2), counter_value)
    begin
        if (rising_edge(control_register(2))) then
            counter_reset <= '0';
            counter_clock_enable <= '1';
            start <= '1';
        elsif (counter_value = x"0000ffff") then
            start <= '0';
            counter_clock_enable <= '0';
            counter_reset <= '1';
            control_register(2) <= '0';
        end if;
    end process;

This is not good code, so I have no idea what the synthesisor made of it. Did you look at the RTL and technology diagram?

You should clock this with "clock", and make an edge detector circuit with control_register(2) -

process(clock)
begin
if rising_edge(clk) then
  control_register2_r <= control_register(2);
  if control_register2_r = '0' and control_register(2) = '1' then -- you have a rising_ege on the signal

Do you have a testbench to test this code in the simualtor?

And as you're trying to improve your VHDL skills - stop using std_logic_arith and std_logic_unsigned. They are non-standard VHDL libraries. Use numeric_std instead.