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Altera_Forum's avatar
Altera_Forum
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15 years ago

Gate-level simulation mentions setup/hold violations

Hi.

I'm trying to perform a gate level simulation of my design. Synthesis report doesn mention any kind of setup/hold violation. Nevertheless, when simulation the design in modelsim, i get a lot of messages similar to the below:

# Note : StratixII PLL locked to incoming clock# Time: 116209 Instance: testbench.d3.clkgen0_a_astrat2_av_asdclk_pll_a_asden_aaltpll0_apll# ** Error: /home_ext/ecco/grlib-gpl-1.0.22-b4075/designs/leon3-altera-ep2s60-sdr/stratixii_atoms.v(1658): $hold( posedge clk &&& sloaddata:1159477 ps, adatasdata:1159509 ps, 200 ps );# Time: 1159509 ps Iteration: 0 Instance: /testbench/d3/a_amg2_asr1_ar_adata_a27_a# ** Error: /home_ext/ecco/grlib-gpl-1.0.22-b4075/designs/leon3-altera-ep2s60-sdr/stratixii_atoms.v(1658): $hold( posedge clk &&& sloaddata:1159475 ps, adatasdata:1159556 ps, 200 ps );

(...)

The gate level simulation never ends though...

Any ideas of what is wrong?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Multiple possibilites come to mind

    a) you've not properly constrained your design, timming wise

    b) your testbench does not comply with the constraints you've specified. For example, if your testbench uses a faster clock than what you've constrained your design for.

    c) you're hitting a bug or limitation of the STA tool.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    b) your testbench does not comply with the constraints you've specified. For example, if your testbench uses a faster clock than what you've constrained your design for.

    --- Quote End ---

    Doesn't really explain a hold violation...
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    In FPGAs, hold violations are usually due to clock skew and are usually related to ripple clocks or gated clocks.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hello,

    Actually, I have quite the same issue: I have one timing violations located into the stratixii_atoms.v file.

    In my waveform window, a red triangle shows up and says: "C:/altera/90/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1572): $hold(posedge clk &&& reset:36531706 ps, ena:36531736 ps, 200 ps);".

    And the line 1572 of the stratixii_atoms.v file is: "$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;".

    Apparently, Modelsim says the hold time is not long enough (30 ps instead of 200 ps), but the stratixii_atoms.v file doesn't specify such hold time. Is it a bug ?

    And surprising enough, when I save the messages into a text file, this violation timing doesn't show up anymore.

    Any idea ?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Actually, it appears in the text file also when I save the messages. I didn't see.