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Altera_Forum
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16 years ago

Gate-level simulation mentions setup/hold violations

Hi. I'm trying to perform a gate level simulation of my design. Synthesis report doesn mention any kind of setup/hold violation. Nevertheless, when simulation the design in modelsim, i get a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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b) your testbench does not comply with the constraints you've specified. For example, if your testbench uses a faster clock than what you've constrained your design for.

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Doesn't really explain a hold violation...