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Altera_Forum
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16 years ago

Gate-level simulation mentions setup/hold violations

Hi. I'm trying to perform a gate level simulation of my design. Synthesis report doesn mention any kind of setup/hold violation. Nevertheless, when simulation the design in modelsim, i get a ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

In FPGAs, hold violations are usually due to clock skew and are usually related to ripple clocks or gated clocks.