Gate-level simulation mentions setup/hold violations

Hello,

Actually, I have quite the same issue: I have one timing violations located into the stratixii_atoms.v file.

In my waveform window, a red triangle shows up and says: "C:/altera/90/modelsim_ase/win32aloem/../altera/verilog/src/stratixii_atoms.v(1572): $hold(posedge clk &&& reset:36531706 ps, ena:36531736 ps, 200 ps);".

And the line 1572 of the stratixii_atoms.v file is: "$setuphold (posedge clk &&& reset, ena, 0, 0, ena_viol) ;".

Apparently, Modelsim says the hold time is not long enough (30 ps instead of 200 ps), but the stratixii_atoms.v file doesn't specify such hold time. Is it a bug ?

And surprising enough, when I save the messages into a text file, this violation timing doesn't show up anymore.

Any idea ?