From GAL's to CPLD's

Assuming a simple non-clocked design:

open quartus => file => new => vhdl then enter your design e.g.:

library ieee;
use ieee_std_logic_1164.all;
entity my_design is
port(
      A : in  std_logic_vector(7 downto 0);
      B : in  std_logic_vecor(7 downto 0);
      C : in  std_logic_vecor(7 downto 0);
      D : in  std_logic_vecor(7 downto 0);
      y : out std_logic_vector(7 downto 0)
     );
end entity;
architecture sum_of_products of my_design is
begin
y <= (A and B) or (C and D);
end sum_of_products;

then save your design. Quartus will ask if you want project on this design then follow it.

Finally select your device from top menu or leave it at default for practice... and select compile. you will get bitstream file (pof , ...etc) downloadable through jtag...

Thanks Kaz, that makes it look all so much more familiar :)

I do have some registered outputs. Some from an ext clk on the dedicated imputs, some outputs are to be registered from internal product terms.

Can I assign clocks to output registers as part of a global configuration somewhere, or is it necessary to incorporate the clocking into the VHDL code?

Hi,

you can insert clocked registers anywhere e.g. at inputs, or intermediate products or final outputs:

add this input at top of entity IF:

clk : in std_logic;

to register outputs then insert this after architecture line:

architecture sum_of_products of my_design is

begin

process

begin

wait until clk = '1';

y <= (A and B ) or (C and D);

end process;

end sum_of_products;

OK, I've just got back to this project after dealing with other hot potatoes :-)

Now, I have my signals defined, and (partially) my logic, and I have managed to find the pin assignments editor to assign the signals to the pins.

I am stuck on how to do the 'rest' of the pin configuration. Perhaps it would help if I explained a bot of what I wanted to do....

Most of the logic is combinational, and some signals are just passing through the device to get level shifted!

There is however one slightly fancy bit, connecting to a device with an 8 bit multiplexed 8 bit address/data bus from a non multiplexed bus.

I can extend the non multiplexed bus cycles, so my approach was to simply to pass the address to the output for a time determined by a counter (I have a clock on one of the dedicated clock inputs), and the switch to the data, input or output as required. Essentially I have a (internal) counter that functions as a sequencer for the operations.

So here are the problems I am having trouble solving:

1) On the input/output pins, how do I define the signal which is to determine when the pin goes tri-state?

2) The counter value is only used internally, so I was planning to use the registers that correspond to input pins, something that appears possible to configure looking at the data sheet. But I cannot understand how to do this! (That is the register output is fed back into the PIA and the input level on the corresponding pin is fed back into the PIA on a seperate path).

3) How do I configure things like weak pull ups on the output cells?

Thanks for any help, I am finding the Altera documentation difficult to follow, it's seems to be orientated around a top down FPGA design flow rather than bottom up glue logic design.

My mind is now numb after several hours exposure to manuals and tutorials.

I have made some progress...I have discovered how to configure pull ups in the assignment editor!

I am also beginning to think that maybe I don't need to explicitly configure the macrocells for the 'buried logic' of my counter, maybe Quartus can automatically assign these signals to unused registers?

I still do not have a clue how to control the output enables. I know from the data sheet that the I/O blocks have an OE selector to choose 1 of 10 global OE signals, and that these global OE signals can derive from product terms. But how to configure them? I need to know a) How to select which OE signal is to be used, and b) how to assign a logic expression to the global signal(s).

I expected to find a) in the assigment editor, but alas there does not appear to be that option.

I wonder if there is perhaps something I have not understood about the OE subsystem. Classic PALS such as a 22V10 simply had an extra logic term for each output to control the OE. The more complex arrangements on these CPLD devices do not seem to offer any advantage, at least as I understand how they work. So I wonder if there is something I have missed, I'm sure they weren't made more complicated just for fun!

I'm also amazed that throughout the numerous documents and tutorials I have viewed so far, there is not a single worked example with a CPLD. Even the 'CPLD developers' profile in the tutorial uses FPGA examples!

I seems to me, that you're still thinking you have to specify every logic wire as it's neccessary with PALASM or whatever you used for GAL design entry. But you don't need with HDL design entry, the design compiler will care obout the hardware details, and also tell you, if your design can't be implemented in the present form.

Although there are dedicated low level primitives for I/Os with tristate, you usually specify them in behavioral VHDL code:

PROCESS (DATA, OE)
BEGIN
  IF OE='1' THEN
    pin <= data;
  ELSE
    pin <= 'Z'; 
  END IF;
END PROCESS;

OR use a conditional assignment without a process. The Quartus Editor has language templates, that show the syntax of common VHDL constructs.

--- Quote Start ---

I seems to me, that you're still thinking you have to specify every logic wire as it's neccessary with PALASM or whatever you used for GAL design entry.

--- Quote End ---

You are right of course :) But I am old and grey and having difficulty learning new tricks!

However, that snip of code has been a great revelation to me :)

Essentially you are saying that by assigning 'Z' to an output or buffer signal then the compiler will automatically do the desired work to ensure that the physical pin that has been assigned to that output signal will go tri-state.

How simple :)

I thought those extra states, other than 1 and 0, in std_logic where just used for intermediate elaboration!

So I think I have now solved all my problems. Hope so because I have to get this board working tomorrow, that's why I'm working over the weekend :(

According to device datasheet (EPM3064), macrocells which correspond to pins used as inputs may be used for buried logic (in my case I want to use them for a counter).

However Quartus does not seem to want to allocate them automatically, it says I have none available!

Is there some trick to doing this?