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I seems to me, that you're still thinking you have to specify every logic wire as it's neccessary with PALASM or whatever you used for GAL design entry.
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You are right of course :) But I am old and grey and having difficulty learning new tricks!
However, that snip of code has been a great revelation to me :)
Essentially you are saying that by assigning 'Z' to an output or buffer signal then the compiler will automatically do the desired work to ensure that the physical pin that has been assigned to that output signal will go tri-state.
How simple :)
I thought those extra states, other than 1 and 0, in std_logic where just used for intermediate elaboration!
So I think I have now solved all my problems. Hope so because I have to get this board working tomorrow, that's why I'm working over the weekend :(
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