From GAL's to CPLD's

Assuming a simple non-clocked design:

open quartus => file => new => vhdl then enter your design e.g.:

library ieee;
use ieee_std_logic_1164.all;
entity my_design is
port(
      A : in  std_logic_vector(7 downto 0);
      B : in  std_logic_vecor(7 downto 0);
      C : in  std_logic_vecor(7 downto 0);
      D : in  std_logic_vecor(7 downto 0);
      y : out std_logic_vector(7 downto 0)
     );
end entity;
architecture sum_of_products of my_design is
begin
y <= (A and B) or (C and D);
end sum_of_products;

then save your design. Quartus will ask if you want project on this design then follow it.

Finally select your device from top menu or leave it at default for practice... and select compile. you will get bitstream file (pof , ...etc) downloadable through jtag...