From GAL's to CPLD's

My mind is now numb after several hours exposure to manuals and tutorials.

I have made some progress...I have discovered how to configure pull ups in the assignment editor!

I am also beginning to think that maybe I don't need to explicitly configure the macrocells for the 'buried logic' of my counter, maybe Quartus can automatically assign these signals to unused registers?

I still do not have a clue how to control the output enables. I know from the data sheet that the I/O blocks have an OE selector to choose 1 of 10 global OE signals, and that these global OE signals can derive from product terms. But how to configure them? I need to know a) How to select which OE signal is to be used, and b) how to assign a logic expression to the global signal(s).

I expected to find a) in the assigment editor, but alas there does not appear to be that option.

I wonder if there is perhaps something I have not understood about the OE subsystem. Classic PALS such as a 22V10 simply had an extra logic term for each output to control the OE. The more complex arrangements on these CPLD devices do not seem to offer any advantage, at least as I understand how they work. So I wonder if there is something I have missed, I'm sure they weren't made more complicated just for fun!

I'm also amazed that throughout the numerous documents and tutorials I have viewed so far, there is not a single worked example with a CPLD. Even the 'CPLD developers' profile in the tutorial uses FPGA examples!