From GAL's to CPLD's

I seems to me, that you're still thinking you have to specify every logic wire as it's neccessary with PALASM or whatever you used for GAL design entry. But you don't need with HDL design entry, the design compiler will care obout the hardware details, and also tell you, if your design can't be implemented in the present form.

Although there are dedicated low level primitives for I/Os with tristate, you usually specify them in behavioral VHDL code:

PROCESS (DATA, OE)
BEGIN
  IF OE='1' THEN
    pin <= data;
  ELSE
    pin <= 'Z'; 
  END IF;
END PROCESS;

OR use a conditional assignment without a process. The Quartus Editor has language templates, that show the syntax of common VHDL constructs.