Hi all,I have a project implemented on Quartus Prime 17.1 Standard version on Ubuntu 20.04 using an Arria10 and this project was working fine without any errors. Then I added 2 IP blocks (one custom and one Intel IP) on the Platform Designer and then I started getting the following error message at the Fitter stage (Synthesis goes smoothly):Info (332104): Reading SDC File: 'hps_SOM01/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc' Info (332104): Reading SDC File: 'hps_SOM01/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc' Info (332104): Reading SDC File: 'hps_SOM01/altera_emif_arch_nf_171/synth/hps_SOM01_altera_emif_arch_nf_171_pvs5pia.sdc' Info (332151): Clock uncertainty is not calculated until you update the timing netlist. Critical Warning: get_entity_instances : Could not find any instances of entity hps_SOM01_altera_emif_arch_nf_171_pvs5pia Error: The auto-constraining script was not able to detect any instance for core < hps_SOM01_altera_emif_arch_nf_171_pvs5pia > Error: Make sure the core < hps_SOM01_altera_emif_arch_nf_171_pvs5pia > is instantiated within another component (wrapper) Error: and it's not the top-level for your project Critical Warning (332008): Read_sdc failed due to errors in the SDC filethe `hps_SOM01` is the name of my qsys file, and when I open the generated VHDL file under <project_dir>/hps_SOM01/synth/hps_SOM01.vhd, I cannot see any component that has the string "altera_emif_arch" in it, so it seems like Quartus is looking for a component called hps_SOM01_altera_emif_arch_nf_171_pvs5pia and I'm getting Fitter stage errors because that component is not in use. I have two EMIF (external memory interfaces) in the design, one for the HPS and the other one for the FPGA fabric. I can see that I have EMIF components hps_SOM01_altera_emif_a10_hps_171_gx2mxci and hps_SOM01_altera_emif_171_juqljaq, but not the one mentioned in the error message. I have no clue how to resolve this error (or what the issue is if there is any), any help would be appreciated.Cheers PS: I need to add these IPs for the current version, but I'm already planning a Quartus software update to a more recent version, so please do not recommend a Quartus upgrade.

Yes, the root cause was that there were multiple top level qsys files in the project (copy of each other, but the file names were different) for revisioning. I had to remove the unused qsys file from my qsf file. After that, I could compile the design all the way.

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anonimcs

Contributor

2 years ago

Solved

Fitter Error not able to detect any instance for core

Hi all,

I have a project implemented on Quartus Prime 17.1 Standard version on Ubuntu 20.04 using an Arria10 and this project was working fine without any errors. Then I added 2 IP blocks (one custom and one Intel IP) on the Platform Designer and then I started getting the following error message at the Fitter stage (Synthesis goes smoothly):

Info (332104): Reading SDC File: 'hps_SOM01/altera_avalon_dc_fifo_171/synth/altera_avalon_dc_fifo.sdc'
Info (332104): Reading SDC File: 'hps_SOM01/altera_jtag_dc_streaming_171/synth/altera_avalon_st_jtag_interface.sdc'
Info (332104): Reading SDC File: 'hps_SOM01/altera_emif_arch_nf_171/synth/hps_SOM01_altera_emif_arch_nf_171_pvs5pia.sdc'
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Critical Warning: get_entity_instances : Could not find any instances of entity hps_SOM01_altera_emif_arch_nf_171_pvs5pia
Error: The auto-constraining script was not able to detect any instance for core < hps_SOM01_altera_emif_arch_nf_171_pvs5pia >
Error: Make sure the core < hps_SOM01_altera_emif_arch_nf_171_pvs5pia > is instantiated within another component (wrapper)
Error: and it's not the top-level for your project
Critical Warning (332008): Read_sdc failed due to errors in the SDC file

the `hps_SOM01` is the name of my qsys file, and when I open the generated VHDL file under <project_dir>/hps_SOM01/synth/hps_SOM01.vhd, I cannot see any component that has the string "altera_emif_arch" in it, so it seems like Quartus is looking for a component called hps_SOM01_altera_emif_arch_nf_171_pvs5pia and I'm getting Fitter stage errors because that component is not in use. I have two EMIF (external memory interfaces) in the design, one for the HPS and the other one for the FPGA fabric. I can see that I have EMIF components

hps_SOM01_altera_emif_a10_hps_171_gx2mxci and hps_SOM01_altera_emif_171_juqljaq, but not the one mentioned in the error message.

I have no clue how to resolve this error (or what the issue is if there is any), any help would be appreciated.

Cheers

PS: I need to add these IPs for the current version, but I'm already planning a Quartus software update to a more recent version, so please do not recommend a Quartus upgrade.

Hdl

anonimcs
2 years ago
Yes, the root cause was that there were multiple top level qsys files in the project (copy of each other, but the file names were different) for revisioning. I had to remove the unused qsys file from my qsf file. After that, I could compile the design all the way.

7 Replies

sstrell
Super Contributor
2 years ago
Have you tried manually regenerating the system in PD before recompiling? Those suffixes are randomly generated for IP added to the system design. Refreshing the system and then manually regenerating then recompiling could/should clean it up.
- anonimcs
  Contributor
  2 years ago
  Hi,
  what do you mean by ‘manually regenerating the system in PD’ ? I always regenerated my system because there was this issue, and I always remove db/ and incremental-db/ folders. These didn’t help
sstrell
Super Contributor
2 years ago
I'm not sure why you're deleting the db folders unless you have other issues. That wouldn't help here. Order of operations:
1) Create system in PD and save.
2) Manually generate the system in PD (Generate menu -> Generate HDL).
3) Switch to Quartus and fully compile the design.
It just seems like something is not pointing to the correct files and regenerating those files might fix it.
- anonimcs
  Contributor
  2 years ago
  I still get the same error when I follow these steps. And I don't see any files missing under Project -> Add/Remove Files in Project. I'd see some file names written in italic font and I'd get an error probably much sooner in Analysis & Synthesis stage anyways...
RichardT_altera
Super Contributor
2 years ago
Hi,

May I know if the issue has been resolved and if you still need help with this case?

Regards,
Richard Tan
- anonimcs
  Contributor
  2 years ago
  Yes, the root cause was that there were multiple top level qsys files in the project (copy of each other, but the file names were different) for revisioning. I had to remove the unused qsys file from my qsf file. After that, I could compile the design all the way.
RichardT_altera
Super Contributor
2 years ago
I'm pleased to know that your issue has been resolved.
Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan

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Fitter Error not able to detect any instance for core

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