Fitter : Error PARALLELTERMINATIONCONTROL connected but does not used on-chip termination

Hello,

I am implementing DDR3 sdram controller interface using qsys in Quartus II (13.1). I am able to generate the synthesis for this DDR3 controller in qsys. When I integrate this controller into my top block, I am able to complete the Analysis & Synthesis but it fail at the Fitter(Place & Route).

The errors are

Error (174068): Output buffer atom "bt820_fpga_ddr_top:i_ddr_top|ddr3_16_01:u0|ddr3_16_01_emif_0:emif_0|ddr3_16_01_emif_0_p0:p0|ddr3_16_01_emif_0_p0_memphy:umemphy|ddr3_16_01_emif_0_p0_new_io_pads:uio_pads|ddr3_16_01_emif_0_p0_altdqdqs:dq_ddio[0].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "PARALLELTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination

Error (174068): Output buffer atom "bt820_fpga_ddr_top:i_ddr_top|ddr3_16_01:u0|ddr3_16_01_emif_0:emif_0|ddr3_16_01_emif_0_p0:p0|ddr3_16_01_emif_0_p0_memphy:umemphy|ddr3_16_01_emif_0_p0_new_io_pads:uio_pads|ddr3_16_01_emif_0_p0_altdqdqs:dq_ddio[1].ubidir_dq_dqs|altdq_dqs2_stratixv:altdq_dqs2_inst|extra_output_pad_gen[0].obuf_1" has port "SERIESTERMINATIONCONTROL[0]" connected, but does not use calibrated on-chip termination

I have added assignment

DQ* output termination series 50 ohm with Calibration

DQ* input termination parallel 50 ohm with Calibration

I disable dynamic ODT and ODT in the DDR3 controller.

How do I resolve these type of errors?

Thank,