New Contributor
Occasional ContributorHello - please see attached. In reviewing the documentation, a single-channel interpolation use case is not well documented, and we are discussing internally on how to better articulate this and use the tvalid/tready on the sink side. Currently, the documentation states that it is a pass-thru from the tready on the source side (which is how it is behaving).
If you change your input to align with attached image, it should behave better. This would mean modulating the tvalid input to assert 1-in-80 clock cycles. If you receive in bursts, you should FIFO to holdoff.
New ContributorHi Jeffc,
I had tried this one, this was giving expected number of outputs.
Occasional ContributorTo be clear - does this allow you to move forward right now? The functionality of "tready" is only a pass-through of the tready on the source side (input). Per the documentation, it's not a function of the current status of the internal FIR. So, you need to create your signaling to match the system behavior, which is what I articulated in the drawing. If you are seeing bursts of data coming in, you might need to add a simple FIFO/buffer that pulls data out at the 1-in-80 and absorbs bursts on the write side (not to exceed a net rate of 1-in-80, of course).
Regular Contributor
