I have attached a file . this is my code for 4tap fir filter.but there is a problem.the o/p i get is not getting verified with the formula of fir.y(n)=h(n)*x(n) plzzzzz help me. plzz help!!!!! coding is done using the transpose form of fir filter

I had a quick look at your code. It looks ok to me in principle. To test better check your method and use this: y = filter([h0 h1 h2 h3],1,x); Also check fmax. You have long paths through mult then add

Here are some further notes: Your code is certainly correct and readable (But be careful,I did not simulate it). Regarding fmax, if I assume your FIR is the full project inside an FPGA then you donot have registers at inputs or output and so timing will not find any paths to report. i.e. your design is fully combinatorial and may fail due to variable delay so add registers at inputs/outputs and mult results. Another note: you have inferred mult and add and that is ok but you have not inferred registers between adders in your transpose pipe. It looks a bit unbalanced in that you can equally infer them on the clock edge. Finally your fir is certainly intuitive but don't know what 4 such taps will do in practice. An example application might be digital amplitude predistortion but that is too involved and requires coeff updating.

--- Quote Start --- Here are some further notes: Your code is certainly correct and readable (But be careful,I did not simulate it). Regarding fmax, if I assume your FIR is the full project inside an FPGA then you donot have registers at inputs or output and so timing will not find any paths to report. i.e. your design is fully combinatorial and may fail due to variable delay so add registers at inputs/outputs and mult results. Another note: you have inferred mult and add and that is ok but you have not inferred registers between adders in your transpose pipe. It looks a bit unbalanced in that you can equally infer them on the clock edge. Finally your fir is certainly intuitive but don't know what 4 such taps will do in practice. An example application might be digital amplitude predistortion but that is too involved and requires coeff updating. --- Quote End --- hello, thnx for the reply...this is my basic project work and here im supposed to just simulate it and show the correct o/p which matches with the fir formula. i have put registers to add,mux ..still not working ....help plzzz.

--- Quote Start --- and where is the testbench? --- Quote End --- i dont use any test bench .As a begginer my guide advised me to use vhdl test bench (by default present in xilinx)

fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

19 Replies

Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
yes you should get [0 6 1 -10]

Are you inputting x correctly just after clock edge. can you post how you drive x?
--- Quote End ---

thnx for the quick reply sir,
im unable to paste the snap shot of the timing diagram
plzzz help me seeing this ....
i hve put 0-100ns---low clock
100-200----high clock [ for both of this xin=0]
200-300 ----low clock[xin= -3]
300-400-----high clock[xin= 1]
400-500------low clock[xin= 0]
500-600-------high clock[xin= -2]
plzz reply me fast sir.......

Altera_Forum

Honored Contributor

13 years ago

--- Quote Start ---

thnx for the quick reply sir,

im unable to paste the snap shot of the timing diagram

plzzz help me seeing this ....

i hve put 0-100ns---low clock

100-200----high clock [ for both of this xin=0]

200-300 ----low clock[xin= -3]

300-400-----high clock[xin= 1]

400-500------low clock[xin= 0]

500-600-------high clock[xin= -2]

plzz reply me fast sir.......

--- Quote End ---

I just simulated your code and it works.

I only replaced your DFF with inferred registers: Here is the code(equivalent to yours, so no need to change anything):


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_4tap is
port(   Clk : in std_logic; --clock signal
        --Xin : in signed(7 downto 0); --input signal
        Yout : out signed(15 downto 0)  --filter output
        );
end fir_4tap;
architecture Behavioral of fir_4tap is
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal Xin : signed(7 downto 0) := "00000000";
signal count : unsigned(4 downto 0) := "00000";
begin
--filter coefficient initializations.
--H = .
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
process
begin
wait until Clk = '1';
count <= count + 1;
if count = 0 then
  Xin <= to_signed(0,8);
elsif count = 1 then
  Xin <= to_signed(-3,8);
elsif count = 2 then
  Xin <= to_signed(1,8);
else
  Xin <= to_signed(0,8);
end if;
Q1 <= MCM3;
Q2 <= add_out1;
Q3 <= add_out2;
end process;
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
    if(rising_edge(Clk)) then
        Yout <= add_out3;
    end if;
end process;
    
end Behavioral;

Edit: I noted you are inputting x on high clock then another value on low clock. You should input data at full clock period i.e. low high period.

Altera_Forum

Honored Contributor

13 years ago

--- Quote Start ---

I just simulated your code and it works.

I only replaced your DFF with inferred registers: Here is the code(equivalent to yours, so no need to change anything):


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_4tap is
port(   Clk : in std_logic; --clock signal
        --Xin : in signed(7 downto 0); --input signal
        Yout : out signed(15 downto 0)  --filter output
        );
end fir_4tap;
architecture Behavioral of fir_4tap is
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal Xin : signed(7 downto 0) := "00000000";
signal count : unsigned(4 downto 0) := "00000";
begin
--filter coefficient initializations.
--H = .
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
process
begin
wait until Clk = '1';
count <= count + 1;
if count = 0 then
  Xin <= to_signed(0,8);
elsif count = 1 then
  Xin <= to_signed(-3,8);
elsif count = 2 then
  Xin <= to_signed(1,8);
else
  Xin <= to_signed(0,8);
end if;
Q1 <= MCM3;
Q2 <= add_out1;
Q3 <= add_out2;
end process;
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
    if(rising_edge(Clk)) then
        Yout <= add_out3;
    end if;
end process;
    
end Behavioral;

Edit: I noted you are inputting x on high clock then another value on low clock. You should input data at full clock period i.e. low high period.

--- Quote End ---

thnk u sir... thnk u very much ..........ivl reply u as soon as i simulate the code..

Altera_Forum
Honored Contributor
13 years ago
did u simulate the code that u have sent sir???
Altera_Forum
Honored Contributor
13 years ago
yes and I said that.

You can just drive your inputs as follows:
clk low 0-99, high 100-199
@ 101 ---- xin=0
@ 301 ----xin= -3
@ 401 -----xin= 1
@ 601 ------xin= 0
@ 801 -------xin= -2
Altera_Forum
Honored Contributor
13 years ago
--- Quote Start ---
yes and I said that.

You can just drive your inputs as follows:
clk low 0-99, high 100-199
@ 101 ---- xin=0
@ 301 ----xin= -3
@ 401 -----xin= 1
@ 601 ------xin= 0
@ 801 -------xin= -2
--- Quote End ---

hello sir, i simulated the code...in the timing diagram now there are clock and o/ps (as inputs are given in the code itself) i have put clock high and even tried for low-high clock pluse but the o/p is y=0 only zero.
thanx for the cooperation sir plzz do reply
Altera_Forum
Honored Contributor
13 years ago
if possible plzz upload ur timing diagram snapshot sir
Altera_Forum
Honored Contributor
13 years ago
sir got it sir but y=[0 6 1] only three o/ps
Altera_Forum
Honored Contributor
13 years ago
sir got it ...thnx a lot sir .thnx u very much .tomm is my project submission .nw i can have a very big smile when submitting.....

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fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

19 Replies

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