fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

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yes and I said that.

You can just drive your inputs as follows:

clk low 0-99, high 100-199

@ 101 ---- xin=0

@ 301 ----xin= -3

@ 401 -----xin= 1

@ 601 ------xin= 0

@ 801 -------xin= -2

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hello sir, i simulated the code...in the timing diagram now there are clock and o/ps (as inputs are given in the code itself) i have put clock high and even tried for low-high clock pluse but the o/p is y=0 only zero.

thanx for the cooperation sir plzz do reply