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I just simulated your code and it works.
I only replaced your DFF with inferred registers: Here is the code(equivalent to yours, so no need to change anything):
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fir_4tap is
port( Clk : in std_logic; --clock signal
--Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_4tap;
architecture Behavioral of fir_4tap is
signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');
signal Xin : signed(7 downto 0) := "00000000";
signal count : unsigned(4 downto 0) := "00000";
begin
--filter coefficient initializations.
--H = .
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);
--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;
--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;
process
begin
wait until Clk = '1';
count <= count + 1;
if count = 0 then
Xin <= to_signed(0,8);
elsif count = 1 then
Xin <= to_signed(-3,8);
elsif count = 2 then
Xin <= to_signed(1,8);
else
Xin <= to_signed(0,8);
end if;
Q1 <= MCM3;
Q2 <= add_out1;
Q3 <= add_out2;
end process;
--an output produced at every positive edge of clock cycle.
process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out3;
end if;
end process;
end Behavioral;
Edit: I noted you are inputting x on high clock then another value on low clock. You should input data at full clock period i.e. low high period.
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thnk u sir... thnk u very much ..........ivl reply u as soon as i simulate the code..
Honored Contributor
