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Altera_Forum's avatar
Altera_Forum
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13 years ago

fir filter code in vhdl [plzzzzzz reply as fast as possible plzzzz]

I have attached a file . this is my code for 4tap fir filter.but there is a problem.the o/p i get is not getting verified with the formula of fir.y(n)=h(n)*x(n) plzzzzz help me. plzz help!!!!! ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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yes you should get [0 6 1 -10]

Are you inputting x correctly just after clock edge. can you post how you drive x?

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thnx for the quick reply sir,

im unable to paste the snap shot of the timing diagram

plzzz help me seeing this ....

i hve put 0-100ns---low clock

100-200----high clock [ for both of this xin=0]

200-300 ----low clock[xin= -3]

300-400-----high clock[xin= 1]

400-500------low clock[xin= 0]

500-600-------high clock[xin= -2]

plzz reply me fast sir.......