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Altera_Forum
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12 years ago

Fast Synthesis & Analysis QUARTUS II

Dear all,

I am new to Quartus II 13.1 , when I implement my logic(considerable big custom IP) tool is taking about 15 hours to complete Analysis & Synthesis part.

I enabled i. Smart Compile

ii. Use all Available Processors

iii. almost all Recommended Suggestions by tool

I am unable to find Rapid Recompile Option, and I unable to use Incremental Compilation Options(unable to explore what that options will exactly do) in Settings->Compilation Options -> Incremental Compilation

Please suggest me Some recommended Options Which may reduce my Compilation Time

Thanks in Advance,

Regards,

Rohith

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi Rohith,

    here some tips :

    1. Is your custom IP very complex one ? Especially, does it use a lot of registers and/or rams ?

    2. Your device must be a too little one for your IP. Try to change the device, and take a bigger FPGA and then launch the Synthesis.

    3. Is your computer's ram enough for Quartus II tools ?

    regards,
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Long synthesis times are usually because you have some ram (sounds like a lot of ram) being implemented in logic. Does your design use a lot of ram? how are you implementing it?

    I had a complex design for a stratix 4 take 40 mins for synthesis, and that is the longest synth I have ever seen. If I ever see more than this, then I know there is a problem in the design.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Long synthesis times are usually because you have some ram (sounds like a lot of ram) being implemented in logic. Does your design use a lot of ram? how are you implementing it?

    I had a complex design for a stratix 4 take 40 mins for synthesis, and that is the longest synth I have ever seen. If I ever see more than this, then I know there is a problem in the design.

    --- Quote End ---

    yes, tricky, one of my module is SRRC filter with coefficient reload option , as per my observation it is mapping lot of ram instances during synthesis(am using Altera FIR IP core for this).

    My Analysis & Elaboration completed in 2 hours, but synthesis taking lot of time(even after 15 hrs it is still 10% remained)

    (sounds like a lot of ram) I unable to explore the context of the sentence, tricky ??

    I am using Cyclone III 3c120f484I7 as my target FPGA

    Thanks for your valuable suggestions.

    Regards,

    Rohith
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Hi Rohith,

    here some tips :

    1. Is your custom IP very complex one ? Especially, does it use a lot of registers and/or rams ?

    2. Your device must be a too little one for your IP. Try to change the device, and take a bigger FPGA and then launch the Synthesis.

    3. Is your computer's ram enough for Quartus II tools ?

    regards,

    --- Quote End ---

    Hi Arriacinq,

    yes, one of my module is SRRC filter with coefficient reload option , as per my observation it is mapping lot of ram instances during synthesis(am using Altera FIR IP core for this).

    My Analysis & Elaboration completed in 2 hours, but synthesis taking lot of time(even after 15 hrs it is still 10% remained)

    I am using Cyclone III 3c120f484I7 as my target FPGA

    Thanks for your valuable suggestions.

    Regards,

    Rohith
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    My PC ram is 8 GB, I think it is more than sufficient, but my C drive has only 2 GB free space does it Effect

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    This SRRC filter - did you write it? Have you tried to compile it in isolation? If you compile your components separately you can find the culprit thats causing the slow synthesis and then investigate it.

    Are the RAMs inferred or are they from the megawizard?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I just wonder what kind of OS you are using.

    In my case, Device is Cyclone IV EP4CGX150 and when I switched 32 bit Quartus/Windows XP

    to 64 bit Quartus/Windows 7, compile times become very fast.

    As you know 32 bit OS can not handle large PC rams effectively.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    It is unlikely to be the OS. If there wasnt enough memory, it would just throw an out of memory error.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    This SRRC filter - did you write it? Have you tried to compile it in isolation? If you compile your components separately you can find the culprit thats causing the slow synthesis and then investigate it.

    Are the RAMs inferred or are they from the megawizard?

    --- Quote End ---

    Hi Tricky,

    SRRC filter is designed with the help of FIR-mega wizard function , since it is a mega wizard, I have not compiled it in Isolation, all RAMs used by me are from Mega wizard only
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    If memory was not enough, the OS would "swap" using a very big file on the drive.... and it becomes very very slow.... with huge drive read/write operations.

    Moreover quartus writes temporary files when compiling.

    2GB of free drive space may affect compilation time.

    A long compilation time is due to bad design too : very long datapaths, dividers, MUX that do not cover all possibilities, multicycle, cross clock domain, inferred RAMs (already said), combinational loop (latches :-( )...

    i have a case where "comodo antivirus+defense plus" puts quartus executable in a sandbox, not only compilation is longerbut the results can't be used !