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Long synthesis times are usually because you have some ram (sounds like a lot of ram) being implemented in logic. Does your design use a lot of ram? how are you implementing it?
I had a complex design for a stratix 4 take 40 mins for synthesis, and that is the longest synth I have ever seen. If I ever see more than this, then I know there is a problem in the design.
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yes, tricky, one of my module is SRRC filter with coefficient reload option , as per my observation it is mapping lot of ram instances during synthesis(am using Altera FIR IP core for this).
My Analysis & Elaboration completed in 2 hours, but synthesis taking lot of time(even after 15 hrs it is still 10% remained)
(sounds like a lot of ram) I unable to explore the context of the sentence, tricky ??
I am using Cyclone III 3c120f484I7 as my target FPGA
Thanks for your valuable suggestions.
Regards,
Rohith
Honored Contributor
