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Altera_Forum
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12 years ago --- Quote Start --- Hi Rohith, here some tips : 1. Is your custom IP very complex one ? Especially, does it use a lot of registers and/or rams ? 2. Your device must be a too little one for your IP. Try to change the device, and take a bigger FPGA and then launch the Synthesis. 3. Is your computer's ram enough for Quartus II tools ? regards, --- Quote End --- Hi Arriacinq, yes, one of my module is SRRC filter with coefficient reload option , as per my observation it is mapping lot of ram instances during synthesis(am using Altera FIR IP core for this). My Analysis & Elaboration completed in 2 hours, but synthesis taking lot of time(even after 15 hrs it is still 10% remained) I am using Cyclone III 3c120f484I7 as my target FPGA Thanks for your valuable suggestions. Regards, Rohith