Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorFalse path question - internal counter bit vs FSM state bit
Dear Altera Forum members...
This is my first post here :) I have a sub-circuit that consists of a binary up-counter (LPM_counter) with asynchronous reset and count enable, and a comparator (LPM_compare). The sub-circuit compares an input 5-bit vector to the count value and sets an output flag if the count value is greater-or-equal to the input data value. This flag is used as a control bit to a finite state machine. When running the TimeQuest timing analyzer tool in Quartus, I get setup timing violations with worst-case timing paths that involve the q[1]-bit and states of the FSM. My question is whether or not I can set these as false paths https://alteraforum.com/forum/attachment.php?attachmentid=14298&stc=1 The figure shows how the TimeQuest labels the nodes that violate the setup timing. I was thinking that since the timing violations does not involve the flag used to control the state transitions, I can set the shown paths as false paths... Please comment. Regards Ronny12 Replies
Altera_ForumThe failing path is between the counter and state machine via the compare. Is it possible to pipeline the compare?
The Max devices are not very fast, so I can only assume the compare is a little too much in the path.- Altera_Forum--- Quote Start --- The failing path is between the counter and state machine via the compare. Is it possible to pipeline the compare? The Max devices are not very fast, so I can only assume the compare is a little too much in the path. --- Quote End --- Thank you so much. I appreciate the comment "the Max devices are not very fast"... Regarding pipelining, does this involve synchronizing the output of the compare to the clock, just prior to using as the FSM control signal ? I.e, connect it to the data port of a D flip-flop, and connect the output port of that same D flip-flop to the flag input port of the FSM ?
