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Altera_Forum
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8 years ago

False path question - internal counter bit vs FSM state bit

Dear Altera Forum members... This is my first post here :) I have a sub-circuit that consists of a binary up-counter (LPM_counter) with asynchronous reset and count enable, and a comparator (LP...
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Altera_Forum
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8 years ago

The failing path is between the counter and state machine via the compare. Is it possible to pipeline the compare?

The Max devices are not very fast, so I can only assume the compare is a little too much in the path.