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Honored Contributor
Honored ContributorFalse path question - internal counter bit vs FSM state bit
Dear Altera Forum members... This is my first post here :) I have a sub-circuit that consists of a binary up-counter (LPM_counter) with asynchronous reset and count enable, and a comparator (LP...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- The failing path is between the counter and state machine via the compare. Is it possible to pipeline the compare? The Max devices are not very fast, so I can only assume the compare is a little too much in the path. --- Quote End --- Thank you so much. I appreciate the comment "the Max devices are not very fast"... Regarding pipelining, does this involve synchronizing the output of the compare to the clock, just prior to using as the FSM control signal ? I.e, connect it to the data port of a D flip-flop, and connect the output port of that same D flip-flop to the flag input port of the FSM ?
