Hi all, When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me out ~

The errors are rather clear: your design is too big for that device. I believe you have already check the right device is selected, right? Then, are you sure your VHDL project should actually fit into it? Maybe you badly instantiated some components and the design generates a lot of extra logic you actually don't need. Or maybe you defined some memory components with a width not matching the fpga memory blocks width and this unexpectedly waste resources. Regards

No routes are a little different than general no-fits. (I think of no-fits as the ones where the design uses more than 100% of the resources). What's the average and peak routing utilization? Some things that can cause this: - High Logic Utilization but still below 100%. There's kind of a peak where a design might not use 100% but is unroutable. - Low fitter effort. For example if you set the fitter effort level to Fast Fit, that can cause a no-fit. - Large hold requirements(this is usually a mistake in multicycle constraints, where users enter multicycle -setup constraints but no corresponding -hold requirements.) In the fitter report look for "Estimated Delays added for hold requirement" (It's something like that.)

There is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal?

--- Quote Start --- There is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal? --- Quote End --- Hi, looks to me that at least parts of the design are not easy to synthesize. Any timing constrains set ? Which FPGA device are you using ? Kind regards GPK

Im using Cyclone III EP3C120F780I7. under what circumstances the code will be hard to synthesize? will that lead to failure in routing the signals?

Failed to route the following signal | Altera Community

26 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Synthesizing 99K LEs should take an hour or two. If something was difficult, maybe double that. There is no way it should take a day. If it's due to reductions, you want it to do that because the design would most likely be many times larger(if that's the problem). As recommended, start making sub-projects of smaller hierarchies and benchmark those(synthesis times, how large they are, etc.) and see if there is a problem area. If you can send the design, might be worth a Service Request with Altera.
--- Quote End ---

I have discovered that there is one part of the design that took up a very long synthesizing time. It involved 6 * 1681 amount of small submodules. any advice on this?
Altera_Forum
Honored Contributor
14 years ago
Is each module less than 10 LUTs? It would have to be for the final design to be 99K. Or are they really something "much larger" that gets reduced?
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Is each module less than 10 LUTs? It would have to be for the final design to be 99K. Or are they really something "much larger" that gets reduced?
--- Quote End ---

each of the small module is 13 LEs only. But i need 6x1681 of it. So end up a bigger design and the synthesizer (took a whole day) reduced it down to 99K. Is it something like that possible?
Altera_Forum
Honored Contributor
14 years ago
It shouldn't. I believe hierarchy actually makes things easier. (It's the large flat designs that I think synthesis sometimes burns time looking for optimizations. Not positive though). You really need to break it up and see what happens.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
It shouldn't. I believe hierarchy actually makes things easier. (It's the large flat designs that I think synthesis sometimes burns time looking for optimizations. Not positive though). You really need to break it up and see what happens.
--- Quote End ---

alright! thank you very much. i will spend some time restructure my design.

but im still having trouble solving the "failed to route the following signals" any advice for this problem?
Altera_Forum
Honored Contributor
14 years ago
Attach your .fit.rpt and I'll take a quick look(2 minutes). Note that routability is not purely a function of how many LEs a design is. A giant shift-register is trivial to route, but if the whole design was a cross-bar mux, it's extremly difficult. Most designs fall somewhere in between. Is your design one of those where "everything talks to everything", or are these 6x1681 blocks pretty serial in nature(the output of one feeds the input of the next one, etc.)
Altera_Forum
Honored Contributor
14 years ago
i would say my design is those "everything talks to everything". my design is at my workplace. i will attach the file tomorrow! i would really appreciate your help here. thanks
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Attach your .fit.rpt and I'll take a quick look(2 minutes). Note that routability is not purely a function of how many LEs a design is. A giant shift-register is trivial to route, but if the whole design was a cross-bar mux, it's extremly difficult. Most designs fall somewhere in between. Is your design one of those where "everything talks to everything", or are these 6x1681 blocks pretty serial in nature(the output of one feeds the input of the next one, etc.)
--- Quote End ---

pls find the attached. thank you !
ecc_41.fit.rpt.txt725 KB
Altera_Forum
Honored Contributor
14 years ago
Are you sure the 24 horus is synthesis? It seems like the fitter is taking a long time(which is expected for something that is hard to route).
First pass shows:
Info: Average interconnect usage is 89% of the available device resources
Info: Peak interconnect usage is 152%
Third and final pass shows:
Info: Average interconnect usage is 68% of the available device resources
Info: Peak interconnect usage is 96% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11

What is the design doing? It has 99,000 LUTs and only 164 registers? It's the "everything talks to everything" topology that makes this design significanly more routing intensive then most designs. Sorry, but I don't think this is going to route as-is, and really don't know what could be done to make it better.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Are you sure the 24 horus is synthesis? It seems like the fitter is taking a long time(which is expected for something that is hard to route).
First pass shows:
Info: Average interconnect usage is 89% of the available device resources
Info: Peak interconnect usage is 152%
Third and final pass shows:
Info: Average interconnect usage is 68% of the available device resources
Info: Peak interconnect usage is 96% of the available device resources in the region that extends from location X23_Y0 to location X33_Y11

What is the design doing? It has 99,000 LUTs and only 164 registers? It's the "everything talks to everything" topology that makes this design significanly more routing intensive then most designs. Sorry, but I don't think this is going to route as-is, and really don't know what could be done to make it better.
--- Quote End ---

hmmm...alright thank you very much. i will restructure my design and break it down to smaller submodules. =)

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Failed to route the following signal

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