Hi all, When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me out ~

The errors are rather clear: your design is too big for that device. I believe you have already check the right device is selected, right? Then, are you sure your VHDL project should actually fit into it? Maybe you badly instantiated some components and the design generates a lot of extra logic you actually don't need. Or maybe you defined some memory components with a width not matching the fpga memory blocks width and this unexpectedly waste resources. Regards

No routes are a little different than general no-fits. (I think of no-fits as the ones where the design uses more than 100% of the resources). What's the average and peak routing utilization? Some things that can cause this: - High Logic Utilization but still below 100%. There's kind of a peak where a design might not use 100% but is unroutable. - Low fitter effort. For example if you set the fitter effort level to Fast Fit, that can cause a no-fit. - Large hold requirements(this is usually a mistake in multicycle constraints, where users enter multicycle -setup constraints but no corresponding -hold requirements.) In the fitter report look for "Estimated Delays added for hold requirement" (It's something like that.)

There is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal?

--- Quote Start --- There is one thing I would like to mention which is my project actually took more than a day to complete just analysis and synthesizing. It took up 99014 LEs. So is the long analysis and synthesizing normal? --- Quote End --- Hi, looks to me that at least parts of the design are not easy to synthesize. Any timing constrains set ? Which FPGA device are you using ? Kind regards GPK

Im using Cyclone III EP3C120F780I7. under what circumstances the code will be hard to synthesize? will that lead to failure in routing the signals?

Failed to route the following signal | Altera Community

26 Replies

Altera_Forum
Honored Contributor
14 years ago
FYI, FPGAs are designed with a routing density that should allow almost every design to fit. They don't put more than is generally necessary since that makes the devices more expensive. So designs that are "outliers" in that they use significantly more routing wires/LE, such as this, will have problems. As I said, having more than 600 LEs/Register is highly unusual. (And note that I'm not saying wrong, just unusual).
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
FYI, FPGAs are designed with a routing density that should allow almost every design to fit. They don't put more than is generally necessary since that makes the devices more expensive. So designs that are "outliers" in that they use significantly more routing wires/LE, such as this, will have problems. As I said, having more than 600 LEs/Register is highly unusual. (And note that I'm not saying wrong, just unusual).
--- Quote End ---

so those having more routing wires/LEs should use ASIC instead?
Altera_Forum
Honored Contributor
14 years ago
Using an ASIC is usually based on a whole other set of requirements(volume, pricing, power, speed, and if you have the tools/expertise to develop an ASIC). And note that just having a lot of LUTs/Reg doesn't mean it will use a lot of routing. It's the everything talks to everything nature of this design. In this case, it just means you may need a larger part or something like that. Also note that Stratix series should have more routes available, so that's another option.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
Using an ASIC is usually based on a whole other set of requirements(volume, pricing, power, speed, and if you have the tools/expertise to develop an ASIC). And note that just having a lot of LUTs/Reg doesn't mean it will use a lot of routing. It's the everything talks to everything nature of this design. In this case, it just means you may need a larger part or something like that. Also note that Stratix series should have more routes available, so that's another option.
--- Quote End ---

thank you for the advice =)
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
What is the design doing? It has 99,000 LUTs and only 164 registers? It's the "everything talks to everything" topology that makes this design significanly more routing intensive then most designs. Sorry, but I don't think this is going to route as-is, and really don't know what could be done to make it better.
--- Quote End ---

I guess ECC is referring to elliptical curves cryptography?

To add some more guesses about the problems showing up: The said LUT to register relation indicates that you are implementing very complex LE chains without breaking them by pipeline registers. This suggests huge logic delays and low effective design speed.

Looks like an approach to implement an algorithm fully parallel that should be better realized in a partly sequential manner.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
I guess ECC is referring to elliptical curves cryptography?

To add some more guesses about the problems showing up: The said LUT to register relation indicates that you are implementing very complex LE chains without breaking them by pipeline registers. This suggests huge logic delays and low effective design speed.

Looks like an approach to implement an algorithm fully parallel that should be better realized in a partly sequential manner.
--- Quote End ---

yes it elliptical curve crypto.

yea, i intend to do a pure combinatorial circuit without any pipelinining. seems like it's not an effecient design. alright, i will try to change it to partly sequential. thanks for the advice

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Failed to route the following signal

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