Failed to route the following signal

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FYI, FPGAs are designed with a routing density that should allow almost every design to fit. They don't put more than is generally necessary since that makes the devices more expensive. So designs that are "outliers" in that they use significantly more routing wires/LE, such as this, will have problems. As I said, having more than 600 LEs/Register is highly unusual. (And note that I'm not saying wrong, just unusual).

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so those having more routing wires/LEs should use ASIC instead?