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Altera_Forum's avatar
Altera_Forum
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14 years ago

Failed to route the following signal

Hi all, When I performed a full compilation on my vhdl project, I have the following errors: 1- failed to route the following signal 2- cant fit design in device Please help me ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

It shouldn't. I believe hierarchy actually makes things easier. (It's the large flat designs that I think synthesis sometimes burns time looking for optimizations. Not positive though). You really need to break it up and see what happens.