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mbilal101's avatar
mbilal101
Icon for New Contributor rankNew Contributor
2 years ago

Failed to create JIC file from stratix 10 latest GSRD

AFAIK, the default ghrd_1sx280lu2f50e2vg_hps.sof file does not come with an external JTAG connection, correct?

To enable the external JTAG connection via the Mictor 38 JTAG connector on the HPS daughter card, the GHRD FPGA design needs to be rebuilt by routing HPS DAP to HPS pins instead of SDM pins.

We were able to achieve this using Quartus Pro v19.3 and GHRD for the 2019.10 version.

Now, we are attempting to do the same thing using the latest GSRD 23.1 version, assuming that it comes with the latest updates, a more efficient design, and the latest u-boot. For this specific reason, we renewed and purchased our floating license to rebuild the design with the latest Quartus Pro 23.1 version for the external JTAG connection.

I can compile the latest GSRD with the latest Quartus Pro, but it is generating a time-limited ghrd_1sx280lu2f50e2vg_time_limited.sof file. As a result, we are unable to create the JIC file due to this time-limited IP component, which is causing the following error. This is a significant disappointment

Error(210039): File ghrd_1sx280lu2f50e2vg_time_limited_hps_auto.sof contains one or more time-limited IPs that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.

I noticed that there is an IP component with an OpenCore Plus license type in the assembler report, and as a result, a time-limited sof file is being generated. Does this mean we need to invest more money to rebuild the latest GSRD in order to have access to the external JTAG connection? The previous GSRD version (19.10) did not have this OpenCore Plus IP.

Is there a way to remove these OpenCore Plus IP components from the latest GSRD so that we can continue using the external JTAG connection without having to purchase any new licenses?

6 Replies

  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Apologies for the late reply.

    There was some error in the case tracking and I have missed out this case.


    Let me get back to you as soon as possible.


    Regards

    Jingyang, Teh


    • mbilal101's avatar
      mbilal101
      Icon for New Contributor rankNew Contributor
      2 years ago

      By default, the latest GSRD includes the 2.5Gb Ethernet PHY IP core with an SGMII Ethernet interface, which is licensed under OpenPlus Core (Evaluation type license). However, this IP core only generates a time-limited sof file and cannot create the final JTAG JIC file. Since the our application does not utilize this IP core and instead uses the GMII interface, it is unnecessary and should be removed. Otherwise, a separate license would need to be purchased to compile the design with this IP core. The following procedure outlines how to remove this IP core from the default GSRD:

      1. Select the IP Components tab in the Project Navigator. Search for the keyword "Ethernet" and remove the alt_mge_phy_1 and alt_mge_phy_2 IP components from the project. Additionally, there may be some remaining references where these IP cores are instantiated, which should also be removed.
      2. Build the design, which will result in a failure. Open the file <gsrd-project>/subsys_mge/synth/subsys_mge.v and either comment out or remove the complete instances of alt_mge_phy_1 and alt_mge_phy_2. Please note that this file may not exist before the build. It is worth mentioning that I attempting to remove the IP cores directly from the FPGA design pins but it lead to numerous errors related to incorrect pin configuration. Therefore, I found that alternative method to remove all references to the redundant IP cores.
  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Any update on this case?

    Do you have any new information?


    Regards

    Jingyang, Teh


  • tehjingy_Altera's avatar
    tehjingy_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi


    Since there are no feedback for this thread, I shall set this thread to close pending. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.


    Regards

    Jingyang, Teh