Failed to create JIC file from stratix 10 latest GSRD

By default, the latest GSRD includes the 2.5Gb Ethernet PHY IP core with an SGMII Ethernet interface, which is licensed under OpenPlus Core (Evaluation type license). However, this IP core only generates a time-limited sof file and cannot create the final JTAG JIC file. Since the our application does not utilize this IP core and instead uses the GMII interface, it is unnecessary and should be removed. Otherwise, a separate license would need to be purchased to compile the design with this IP core. The following procedure outlines how to remove this IP core from the default GSRD:

1. Select the IP Components tab in the Project Navigator. Search for the keyword "Ethernet" and remove the alt_mge_phy_1 and alt_mge_phy_2 IP components from the project. Additionally, there may be some remaining references where these IP cores are instantiated, which should also be removed.
   
2. Build the design, which will result in a failure. Open the file <gsrd-project>/subsys_mge/synth/subsys_mge.v and either comment out or remove the complete instances of alt_mge_phy_1 and alt_mge_phy_2. Please note that this file may not exist before the build. It is worth mentioning that I attempting to remove the IP cores directly from the FPGA design pins but it lead to numerous errors related to incorrect pin configuration. Therefore, I found that alternative method to remove all references to the redundant IP cores.