--- Quote Start ---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;
entity witness is
generic (
MAX_DEPTH : integer := 9; -- max tree depth
HASH_LENGTH : integer := 2; -- hash length in words
BLOCK_LENGTH : integer := 32; -- block length in words
MEM_WIDTH : integer := 16); -- word width
port (
clk : in std_logic;
rstb : in std_logic; -- active low async reset
start : in std_logic; -- start bit
path_depth : in std_logic_vector(MAX_DEPTH-1 downto 0); -- one hot
w_beta : in std_logic_vector(MAX_DEPTH-1 downto 0); -- selected node;
ptr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- pointer value
wr : out std_logic_vector(MEM_WIDTH-1 downto 0); -- enable ptr writre
status : out std_logic); -- finish bit
end entity witness;
architecture arch of witness is
signal curr_depth, curr_depth_buf, curr_depth_bufbuf : unsigned(MAX_DEPTH-1 downto 0);
signal leftright, leftright_buf, status_tmp, leaf : std_logic; -- 1 is goto branch 1
signal shift_w, shift_p, w_addr, p_addr : unsigned(MEM_WIDTH-1 downto 0);
constant root_addr : integer := 2**(MAX_DEPTH)-1;
begin -- architecture arch
-- purpose: Buffer some signals
buf: process (clk, rstb) is
begin -- process buf
if clk'event and clk = '1' then -- rising clock edge
curr_depth_bufbuf <= curr_depth_buf;
curr_depth_buf <= curr_depth;
leftright_buf <= leftright;
end if;
end process buf;
leftright <= '0' when (unsigned(w_beta) and curr_depth) = (9 downto 0 => '0') else '1'; --bitwise
leaf <= path_depth(MAX_DEPTH-1) and curr_depth_buf(0);
ptr <= std_logic_vector(w_addr);
wr <= std_logic_vector(resize(curr_depth_bufbuf, MEM_WIDTH));
-- purpose: shift current depth
-- type : sequential
shift_depth: process (clk, rstb) is
begin -- process shift_depth
if clk'event and clk = '1' then -- rising clock edge
if start = '0' then
curr_depth <= unsigned(path_depth);
else
curr_depth <= '0' & curr_depth(MAX_DEPTH-1 downto 1); --which level we are in the tree
end if;
end if;
end process shift_depth;
-- purpose: Compute shifts
shift_proc: process (clk, start) is
begin -- process
if start = '0' then
shift_p <= (others => '1');
shift_w <= (others => '0');
p_addr <= to_unsigned(root_addr, 16) + to_unsigned(hash_length, 16);
elsif clk'event and clk = '1' then -- rising clock edge
if leftright = leftright_buf then
shift_p <= resize(2*shift_left, MEM_WIDTH);
shift_w <= shift_w + shift_p;
else
shift_w <= resize(2*shift_left, MEM_WIDTH);
shift_p <= shift_w + shift_p;
end if;
p_addr <= p_addr - shift_p*hash_length;
if leaf='0' then
w_addr <= p_addr - shift_w*hash_length;
else
w_addr <= p_addr - (unsigned(w_beta)/2)*hash_length - (shift_w-(unsigned(w_beta)/2))*block_length;
end if;
end if;
end process;
-- purpose: Handle status bit
status_proc: process (clk, rstb) is
begin -- process status_proc
if rstb = '0' then -- asynchronous reset (active low)
status_tmp <= '0';
elsif clk'event and clk = '1' then -- rising clock edge
status_tmp <= status_tmp or curr_depth_bufbuf(0);
end if;
end process status_proc;
status <= status_tmp;
end architecture arch;
--- Quote End ---
here is my code can plz clarify me more about the process "compute shift"
Honored Contributor
