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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

expression has 2 elements, but must have 4 elements

Hey guys,

This is trashing my brain, please help. 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shifter  IS
PORT (
        A: IN UNSIGNED (1 downto 0);
        B: IN UNSIGNED (1 downto 0);
        OUTPUT : OUT UNSIGNED (3 downto 0)
        );
END shifter;
ARCHITECTURE identifier OF shifter IS
BEGIN
    process(A,B)
    variable C : INTEGER range 0 to 15;
    BEGIN
            C := TO_INTEGER(B);
            OUTPUT <= A sll C;
        END PROCESS;
END identifier;
Logs: 

Error (10344): VHDL expression error at shift.vhd(23): expression has 2  elements, but must have 4 elements
which means this line

OUTPUT <= A sll C;

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think you are making some confusion with types.

    Infact:

    A and B are defined as an array of 2 unsigned elements

    OUTPUT is defined as an array of 4 unsigned elements

    OUTPUT <= A sll C shifts left A by C (=B) bits

    I'm not a vhdl expert but I think than sll must always operate on a bit vector (error1: here you have an unsigned int vector) ; then you assign the result to a different size array (error2: A size 2, OUTPUT size 4)

    Probably you are confusing array dimensions with ranges.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks that worked.

    I only had to make this change

    A: IN UNSIGNED (3 downto 0);
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    I think you are making some confusion with types.

    Infact:

    A and B are defined as an array of 2 unsigned elements

    OUTPUT is defined as an array of 4 unsigned elements

    OUTPUT <= A sll C shifts left A by C (=B) bits

    I'm not a vhdl expert but I think than sll must always operate on a bit vector (error1: here you have an unsigned int vector) ; then you assign the result to a different size array (error2: A size 2, OUTPUT size 4)

    Probably you are confusing array dimensions with ranges.

    --- Quote End ---

    sll is defined for bit_vector, unsigned and signed.

    Another way to may it work would have been:

    output <= ("00" & A) sll C;